Double patterning and hypernumerical aperture immersion lithography mark amirtharaj zach kruder enee416 111711. To enable dpt, a layout decomposition tool is first used to split the. Double patterning summary lithoetchlithoetch first double patterning technique successfully reduces k 1below previous limit doubles the processing steps, so doubles the cost and reduces throughput requires a hard mask suffers from mask overlay issues c. Double patterning can be implemented in three ways. Double patterning technology dpt, spacer patterning technologies spt, cd control, cd budget, design for manufacturability dfm 1. Introduction the use of doublemultiplepatterning dpmp optical lithography for sub20nm technologies has become inevitable manuscript received july 10, 2012.
Globalfoundries is also making greater use of double patterning at 20nm. Double patterning technology dpt is the best alternative to achieve 3x nand flash node by 193nm immersion lithography before entering euv regime. As optical lithography advances to 32 nm technology node and beyond, double patterning technology dpt has emerged as an attractive solution to circumvent the fundamental optical limitations. As a practical solution, pitch doubling technique known as double patterning lithography. Although the cost of ownership of a combined method is an issue, the huge opportunity costs of any ngl in its current state make dp lithography dpl. One or more techniques or systems for determining double patterning technology dpt layout routing compliance are provided herein. Double patterning technology friendly detailed routing.
Node sizes of transistors made by companies like intel, toshiba, ibm, and amd are around 32nm and 22nm with the help of hypernumerical aperture immersion lithography systems. Two primary techniques for patterning additive and subtractive processes. Double patterning for 32nm and beyond linkedin slideshare. Double patterning technology dpt has emerged as the most hopeful candidate for the next technology node of the itrs roadmap 1. The goal of a dpt decomposer is to decompose the entire layout on each layer onto two masks. Various double patterning techniques resist freeze process lithography performance of jsr freeze process 32nm ls formation and etching freezing process for 2d logic patterning contact hole formation by freezing process summary. Double patterning also includes a spacer technique called selfaligned double patterning sadp.
Pdf simultaneous layout migration and decomposition for. Double exposure and double patterning have emerged as leading candidates to fill the technology gap between water immersion and euv lithography. As the technology nodes scale down to 22nm and beyond, double patterning lithography dpl has been considered as a practical solution for layout manufacturing. It is expected to be necessary for the 10 nm and 7 nm node semiconductor processes and beyond. Us9317650b2 double patterning technology dpt layout. A method of making a device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer to form a first photoresist pattern comprising a first grid, rendering the first photoresist pattern insoluble to a solvent, forming a second photoresist layer over the first photoresist pattern, patterning the second photoresist layer to form a second. To compensate, chipmakers are using advanced techniques like doublequadruple and spacerbased patterning, involving multiple masks and process sets. Pdf double patterning technology dpt is a most likely lithography solution for 3222 nm technology nodes as of 2008 due to the delay of extreme. Multiple patterning or multipatterning is a class of technologies for manufacturing integrated circuits ics, developed for photolithography to enhance the feature density. Double patterning technology can be classified into two major main streams, however its implementation and especially the details of the process integration vary strongly among the semiconductor company and every manufacturer found his own optimum. By assigning different values to a and b, the pdf takes a variety. Stateoftheart 193 nm tool with a numerical aperture of 1. Cmos technology scaling gate length has not scaled proportionately with device pitch 0.
Interactions of double patterning technology with wafer processing, opc and design flows kevin lucas, chris cork, alex miloslavsky, gerry lukpat, levi barnes, john hapli, john lewellen, greg rollins synopsys vincent wiaux, staf verhaegen imec leuven belgium predictable success imec, leuven, belgium if it moves, chop it in half, then simulate it. It assigns two features to di erent masks if their spacing is less than a prede ned threshold. The most obvious of these is 193nm immersion 193i lithography. Typically, double patterning refers to the lithoetchlithoetch lele pitchsplitting process in the fab, according to mentor graphics. Ruth brain intel fellow, technology and manufacturing group. Dpl has become a strong candidate for 22nm lithography process. As such, double patterning lithography dpl is the most promising option to generate the required lithography resolution, where the target layout is printed with two separate imaging processes.
Therefore, presenters will not be addressing first quarter information during this years program. Pdf double patterning technology friendly detailed. Simultaneous overlay and cd measurement for double. Double patterning at 20nm is one of those big unavoidable changes that it is almost impossible to know too much about. Pads in the right half of the sequence pads 115 have increasing positive overlay shifts fig.
Layout optimizations for double patterning lithography. Process window analysis in a manydimensional space. To realize double patterning lithography, patterns located within a subresolution dis. It will enable designers to develop chips for manufacture on subnanometer process nodes using current optical lithography systems. Transistor performance has been boosted by other means. For the extremely regular arrays of memory chips like e. Alignment method of selfaligned double patterning process. Simultaneous layout migration and decomposition for double patterning technology. Pdf eda solutions for double patterning lithography. The basic idea is that if a pitch of interest is not achievable in a single lithography step, the design is split over two lithography layers in a way that the minimum pitch. Technology and manufacturing day intel technology and manufacturing day 2017 occurs during intels quiet period, before intel announces its 2017 first quarter financial and operating results.
Dpt poses unique demands on critical dimension cd uniformity and overlay control, making the tolerance decrease much faster than. Introduction the use of double multiple patterning dpmp optical lithography for sub20nm technologies has become inevitable manuscript received july 10, 2012. Todays singleexposure, 193nm wavelength lithography reached its physical limit at 40nm halfpitch. Double patterning is a common multiple patterning technique.
Patterning is the backbone of scaling, which has reduced the size of the transistor to where it is today, in turn making modern electronic devices increasingly affordable. Abstractdouble patterning lithography dpl provides an attractive alternative or a. Among different dpl techniques lithoetchlithoetch lele and selfaligned double. Interactions of double patterning technology with wafer. Application of double patterning technology to fabricate. Early test results have demonstrated that key technical challenges to double patterning, such as tight overlap requirements and strict cd control, are being solved, while novel materials for double.
The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. Even as these approaches ease lithography limitations, they create new demands for exceptional process precision and film quality in order to accurately produce the fine, dense features required. Ic validator double patterning signoff technology the principal core technologies required for signoffquality dpt color decomposition are 1 the ability to formulate advanced rules and 2 synthesize those rules with a coloring engine to analyze the decomposability of a layout. Of course in addition to these two big new issues double patterning, ldes there are all the old issues that just get worse, whether design complexity, clock tree synthesis and so on. Double patterning technology description in 1965 gordon moore, cofounder of intel, made an observation that the number of transistors per square inch on integrated circuits doubles approximately every two years since the integrated circuit was invented. Pdf double patterning technology friendly detailed routing. Double patterning technology dpt is one of the main options for printing critical layers at 32nm halfpitch and beyond. Multiple patterning enables chipmakers to image ic designs at 20nm and below.
Double patterning techniques the other way is to decrease the wavelength of the light used in patterning. Nand flash memories, aggressive double patterning technology nodes. Jul 05, 20 globalfoundries is also making greater use of double patterning at 20nm. In the fab, lele requires two separate lithography and etch. Assessing chiplevel impact of double patterninglithography. In dpl, pitch size which limits the patterning resolution, becomes twice than that of single patterning. By david abercrombie, rehab ali, ahmed hamedfatehy, and shetha nolke how the sidsadp process affects your design decisions selfaligned double patterning sadp is an alternative doublepatterning process to the traditional lithoetchlithoetch lele approach used in most advanced production nodes. Double patterning is the only lithography technique to be used for the 32 nm and 22 nm halfpitch nodes in 20082009 and 20112012, respectively, using tools already available today. An alternative choice for sub22nm technology node is dpl 11. In order to achieve this, some version of double patterning dp technology will need to be combined with established techniques. The challenges of double pattering dpbased design are looming large to those customers starting to move to the 20 nm technology node. While many resolution enhancement technologies ret have been developed recently. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. Introduction the accelerating shift toward much smaller patterning sizes in ulsi poses difficulties concerning lithography.
Logic technology development, quality and reliability engineering, dts, intel corporation. Postdecomposition assessment of double patterning layout. Consequently, patterning is also the driving force behind a multitude of advances in semiconductor manufacturing technologies. In 1965 gordon moore, cofounder of intel, made an observation that the number of transistors per square inch on integrated circuits doubles approximately every two years since the integrated circuit was invented. Double patterning for sub28nm ics tech design forum. Technology and manufacturing day 14 nm technology leadership dr. Multiple patterning or multi patterning is a class of technologies for manufacturing integrated circuits ics, developed for photolithography to enhance the feature density. High reliability arf light source for double patterning. The immaturity of next generation technologies means that existing techniques need to be extended in order to solve the 32nm and 22nm halfpitch nodes. Introduction in order to continue technology shrink roadmaps and to provide year by year smaller chips with more functionality, nearly all of the leading edge semiconductor companies have.
Of course, much of the fear and trepidation is simply due to it being something new to learn, and the sense of risk that a move into the unknown can instill. Page 3 complimentary lithography use dipole illumination or alternating psm to form dense linesspaces or sadp for smaller pitch use second lithoetch step to trim ends of lines. Introduction double patterning dp lithography is gaining widespread us e in 32 and sub32nm technology nodes as an extension to immersion lithography. Eda solutions for double patterning lithography semantic scholar. Mentors david abercrombie, dfm program manager for calibre, has written a series of articles detailing the multifaceted impacts of double patterning on advanced node design and verification. Lithoetchlithoetch lele, lithofreezelithoetch lfle, and selfaligned double patterning sadp. At the 14 nm technology node, intel has developed all of the key enablers to.
The principle of double patterning was demonstrated in 1983. Double, triple and quadruple patterning and future lithography. Abstract double patterning technology dpt is a most likely lithography solution for 3222nm technology nodes as of 2008 due to the delay of extreme ultra. Automated tools are rare and manual interaction of the designers is. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. Optimized hfbased highk films new low k barrier materials for sub45nm nodes bilayer darc for 30nm lithography patterning aerial imaging maskbased wafer cdu mapping new design techniques and patterning films enabling double patterning.
At 514, the method 500 comprises determining at least one of a double patterning technology dpt compliance for the pin loop or a dpt violation for the pin loop based on the pin loop value. Expanding the optical lithography to 32nm node and beyond is impossible using existing single exposure systems. This double patterning technique is usually referenced with lithoetchlithoetch lele but other names such as brute force or pitch splitting exist as well. Diffraction based overlay metrology for double patterning technologies 439 2. Intel, meanwhile, uses the technique to a limited degree at 22nm, but has avoided the need to adopt it as widely. Double patterning overlay and cd budget for 32 nm technology node article pdf available in proceedings of spie the international society for optical engineering 6924 march 2008 with 200 reads. Dpt poses unique demands on critical dimension cd uniformity and overlay control, making the tolerance decrease much faster than the rate at which. A study of cd budget in spacer patterning technology. Double patterning is a technique used in the lithographic process that defines the features of integrated circuits at advanced process nodes. Double patterning counters the effects of diffraction in optical lithography, which happens because the minimum dimensions of advanced process nodes are a. Double patterning is a technique that decomposes a single layout into two masks in order to increase pitch size and improve depth of focus df.
Diffraction based overlay metrology for double patterning. Simultaneous overlay and cd measurement for double patterning. Double patterning overlay and cd budget for 32 nm technology node article pdf available in proceedings of spie the international society for optical engineering 6924. Cadence virtuoso layout design environment users manual.
613 1449 847 659 944 15 327 45 956 38 1199 1183 1464 1232 341 677 198 1018 177 541 514 1554 587 293 389 497 136 1438 486 993 673 70 1161 747 1391 337 1117 393 655 1026 1488 872 85 24 289